| PART |
Description |
Maker |
| 74F109 I74F109D I74F109N N74F109D N74F109N 74F109_ |
Positive J-K positive edge-triggered flip-flops F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
From old datasheet system
Positive J-Knot positive edge-triggered flip-flops
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 54HHSC125FD 54HHSC165LD 54HSC74LC 54HST574LC 54QHS |
HSC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14
HSC SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, CQCC20
HSC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
HST/T SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
HSC SERIES, 8-BIT IDENTITY COMPARATOR, INVERTED OUTPUT, CDFP20
HST/T SERIES, 8-BIT ENCODER, CDIP16
HST/T SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, UUC
HSC SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, UUC
HST/T SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDIP24
HST/T SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, CDFP24
HST/T SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CQCC20
HST/T SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14
HST/T SERIES, QUAD 2-INPUT AND GATE, UUC
HSC SERIES, 8-BIT DRIVER, TRUE OUTPUT, CQCC20
HSC SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, CQCC20
|
|
| 5962F9863201VCC 5962F9863201V9A 5962F9863201VXC AC |
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP16
AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16
Radiation Hardened Dual J-K Flip-Flop with Set and Reset 辐射硬化的设置和复位JK触发
|
Intersil Corporation
Intersil, Corp.
|
| 74AUP2G80GD125 74AUP2G80GM125 |
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT996-2 (XSON8U); Container: Reel Pack, Reverse, Reverse AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
Low-power dual D-type flip-flop; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors N.V.
|
| 74LCX74SJ 74LCX74MX_NL 74LCX74 74LCX74BQX 74LCX74M |
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs
Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, QCC14
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor, Corp.
|
| 74AUP1G74GT-G 74AUP1G74GF |
Low-power D-type flip-flop with set and reset; positive-edge trigger AUP/ULP/V SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| MC74HC109DR2 |
HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
|
MOTOROLA INC
|
| ISL6293 ISL6293-2CR-T ISL6293-2CR ISL6293-2CRZ ISL |
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SOIC -40 to 85
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-PDIP -40 to 85
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SO -40 to 85 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO10
Li-ion/Li Polymer Battery Charger Accepting Two Power Sources
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| HEF4013BDB |
4000/14000/40000 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
|
NXP SEMICONDUCTORS
|
| MC100LVEL29DWR2 |
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset 100LVEL SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO20
|
ON Semiconductor
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
|
